Who We are

As a president and founder of 4Silicon Design Service Inc, Masood Khan brings 30 years of IC design experience to start 4Silicon Design Service. Masood began his career in VLSI design in 1983 with Texas Instruments Inc as Layout designer while continuing studies in Electrical Engineering at Texas Southern University in Houston Texas. After completing the degree in Electrical Engineering, Masood joined Application Specific Product group of Texas Instruments as a design engineer where he developed Memory Compiler methodology for DSP and Micro Controller. During his 15 year of service with Texas Instruments, He was assigned in Sun Microsystems in Sunnyvale California for 7 years as Texas Instruments liaison where he contributed to world class high performance SPARC microprocessor series. Masood was Array Design Manager in Hitachi Semiconductor America where he developed Cache memory systems for Supper-H5 microprocessor core. Masood also served as Senior Director in Arcadia Design Service, Director of Memory Technology in Artisan Components, Product Line Manager in Legerity Design and as a Senior Scientist in IBM corporation.
Masood’s major technical expertise are in transistor level custom circuit design and layout of low power and high performance full custom SRAM/CAM, Cache memories, TLB, ROM, Dual Port SRAM and Register Files, Standard cell library, Memory Compilers, data path, timing analysis, clock & power distribution design and functional verification
Masood’s publications and patents
PUBLICATIONS
⦁ 64-KByte Sum-Address-Memory Cache with 1.6ns and 2.6ns latency, ISSCC Dig tech paper Feb, 1998 & IEEE JSSC Vol 33 November 1998
⦁ Universal-Vdd 0.65-2.0V 32kB cache using Voltage-Adopted Timing-Generation Scheme and a Lithographical-Symmetric Cell

PATENTS
Duplicate bit line self-time technique for reliable memory operation; US Patent. 6212117 Hitachi San Jose CA
⦁ Method and apparatus for controlling the timing of pre charge in a content addressable memory; US Patent 7167385 IBM Austin, TX
⦁ Content addressable memory including a dual mode cycle boundary latch; US Patent 7283404 Khan et al. IBM Austin, TX
⦁ Efficient muxing scheme to allow for bypass and array access; US Patent application 2006019829/A1 Sept 7 2006 IBM Austin, TX